VHDL Package not detected by Modelsim

This is Modelsim-Atera output after i run "vmap"

vmap
# Reading modelsim.ini
# "work" maps to directory ./rtl_work.
# "Fir_left_ch" maps to directory ./Fir_left_ch.
# Reading C:/altera_lite/16.0/modelsim_ase/win32aloem/../modelsim.ini
# "std" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../std.
# "ieee" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../ieee.
# "verilog" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../verilog.
# "vital2000" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../vital2000.
# "std_developerskit" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../std_developerskit.
# "synopsys" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../synopsys.
# "modelsim_lib" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../modelsim_lib.
# "sv_std" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../sv_std.
# "altera_mf" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/altera_mf.
# "altera" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/altera.
# "altera_lnsim" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/altera_lnsim.
# "lpm" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/220model.
# "220model" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/220model.
# "maxii" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/maxii.
# "maxv" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/maxv.
# "fiftyfivenm" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/fiftyfivenm.
# "sgate" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/sgate.
# "arriaii" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriaii.
# "arriaii_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriaii_hssi.
# "arriaii_pcie_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriaii_pcie_hip.
# "arriaiigz" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriaiigz.
# "arriaiigz_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriaiigz_hssi.
# "arriaiigz_pcie_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriaiigz_pcie_hip.
# "stratixiv" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/stratixiv.
# "stratixiv_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/stratixiv_hssi.
# "stratixiv_pcie_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/stratixiv_pcie_hip.
# "cycloneiv" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/cycloneiv.
# "cycloneiv_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/cycloneiv_hssi.
# "cycloneiv_pcie_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/cycloneiv_pcie_hip.
# "cycloneive" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/cycloneive.
# "stratixv" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/stratixv.
# "stratixv_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/stratixv_hssi.
# "stratixv_pcie_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/stratixv_pcie_hip.
# "arriavgz" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriavgz.
# "arriavgz_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriavgz_hssi.
# "arriavgz_pcie_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriavgz_pcie_hip.
# "arriav" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/arriav.
# "cyclonev" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/cyclonev.
# "twentynm" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/twentynm.
# "twentynm_hssi" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/twentynm_hssi.
# "twentynm_hip" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/twentynm_hip.
# "fourteennm" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/vhdl/fourteennm.
# "altera_mf_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/altera_mf.
# "altera_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/altera.
# "altera_lnsim_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/altera_lnsim.
# "lpm_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/220model.
# "220model_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/220model.
# "maxii_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/maxii.
# "maxv_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/maxv.
# "fiftyfivenm_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/fiftyfivenm.
# "sgate_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/sgate.
# "arriaii_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriaii.
# "arriaii_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriaii_hssi.
# "arriaii_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriaii_pcie_hip.
# "arriaiigz_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriaiigz.
# "arriaiigz_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriaiigz_hssi.
# "arriaiigz_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriaiigz_pcie_hip.
# "stratixiv_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/stratixiv.
# "stratixiv_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/stratixiv_hssi.
# "stratixiv_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/stratixiv_pcie_hip.
# "stratixv_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/stratixv.
# "stratixv_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/stratixv_hssi.
# "stratixv_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/stratixv_pcie_hip.
# "arriavgz_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriavgz.
# "arriavgz_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriavgz_hssi.
# "arriavgz_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriavgz_pcie_hip.
# "arriav_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriav.
# "arriav_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriav_hssi.
# "arriav_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/arriav_pcie_hip.
# "cyclonev_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cyclonev.
# "cyclonev_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cyclonev_hssi.
# "cyclonev_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cyclonev_pcie_hip.
# "cycloneiv_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cycloneiv.
# "cycloneiv_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cycloneiv_hssi.
# "cycloneiv_pcie_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cycloneiv_pcie_hip.
# "cycloneive_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/cycloneive.
# "twentynm_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/twentynm.
# "twentynm_hssi_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/twentynm_hssi.
# "twentynm_hip_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/twentynm_hip.
# "fourteennm_ver" maps to directory C:/altera_lite/16.0/modelsim_ase/win32aloem/../altera/verilog/fourteennm.