VHDL Package not detected by Modelsim

Thanks i got rid of that error , but now i am getting this error :

-- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package NUMERIC_STD
# -- Loading package audio_codec_i2c_pkg
# -- Compiling entity tb_audio_ctrl_Top
# -- Compiling architecture testing_audio of tb_audio_ctrl_Top
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(54): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(54): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(55): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(55): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(58): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# End time: 14:35:41 on Mar 08,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 5
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs="+acc" tb_audio_ctrl_Top.vhd
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs=""+acc"" tb_audio_ctrl_Top.vhd
# Start time: 14:35:41 on Mar 08,2022
# ** Error: (vsim-19) Failed to access library 'tb_audio_ctrl_Top' at "tb_audio_ctrl_Top".
#
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./Audio_FIR_filter_run_msim_rtl_vhdl.do PAUSED at line 76

Can you show the code lines from the file that are mentioned as having issues?

See attached test bench and do file as well .

Testbench :

-- Testbench for the i2c_audio_ctrl_Top.vhd

LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
USE IEEE.std_logic_arith.ALL;

Library work;
USE work.audio_codec_i2c_pkg.All;

ENTITY tb_audio_ctrl_Top IS
END tb_audio_ctrl_Top;

ARCHITECTURE testing_audio OF tb_audio_ctrl_Top IS
COMPONENT i2c_audio_ctrl_Top
port (
CLOCK_50 : in std_logic;
PUSHB : in std_logic_vector ( 3 downto 0 );
LED : out std_logic_vector ( 3 downto 0 );
SW : in std_logic_vector ( 17 downto 0 );
LEDR : out std_logic_vector ( 17 downto 0 );
LEDG : out std_logic_vector ( 7 downto 0 );
GPIO : out std_logic_vector ( 35 downto 0 ); -- 40-pin Connector
I2C_SCLK : out std_logic;
I2C_SDAT : inout std_logic;
--audio codec ports
AUD_ADCDAT : in std_logic;
AUD_ADCLRCK: out std_logic;
AUD_DACLRCK: out std_logic;
AUD_DACDAT : out std_logic;
AUD_XCK : out std_logic;
AUD_BCLK : out std_logic
);
END COMPONENT;

I'm guessing the simulator doesn't like your use of "us" and "ms" right after a value without a space.

Thanks again for pointing that out , i did get rid of those warnings , but i still get that error :

With in Modelsim in the above attached pic , i noticed that Modelsim only has "Fir_left_ch" , although in vhdl top file i have two Fir ip included one for left and other for right channel . Anyway i right clicked on the tb in the work folder and forced compiled it , and it successfully compiled it and then simulated the tb and it worked .

I still want to get rid of this annoying error which pops up when i start simulating from Quartus i.e "# ** Error: (vsim-19) Failed to access library 'tb_audio_ctrl_Top' at "tb_audio_ctrl_Top".

Why do i have to force compile and simulate the tb

Ahmed,

You probably need to look at below KDB related to your issue

https://www.intel.com/content/www/us/en/programmable/support/support-resources/knowledge-base/solutions/rd02292008_717.html