VHDL Package not detected by Modelsim

Thanks i got rid of that error , but now i am getting this error :

-- Loading package std_logic_arith
# -- Loading package STD_LOGIC_UNSIGNED
# -- Loading package NUMERIC_STD
# -- Loading package audio_codec_i2c_pkg
# -- Compiling entity tb_audio_ctrl_Top
# -- Compiling architecture testing_audio of tb_audio_ctrl_Top
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(54): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(54): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(55): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(55): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# ** Warning: D:/Quartus_projects/i2c_audio_Fir_filtr1p1/source/tb_audio_ctrl_Top.vhd(58): (vcom-1207) An abstract literal and an identifier must have a separator between them.
# End time: 14:35:41 on Mar 08,2022, Elapsed time: 0:00:00
# Errors: 0, Warnings: 5
#
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs="+acc" tb_audio_ctrl_Top.vhd
# vsim -t 1ps -L altera -L lpm -L sgate -L altera_mf -L altera_lnsim -L cycloneive_ver -L cycloneive -L rtl_work -L work -L Fir_left_ch -voptargs=""+acc"" tb_audio_ctrl_Top.vhd
# Start time: 14:35:41 on Mar 08,2022
# ** Error: (vsim-19) Failed to access library 'tb_audio_ctrl_Top' at "tb_audio_ctrl_Top".
#
# No such file or directory. (errno = ENOENT)
# Error loading design
# Error: Error loading design
# Pausing macro execution
# MACRO ./Audio_FIR_filter_run_msim_rtl_vhdl.do PAUSED at line 76