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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL Module simulation

Hi, I'm new to VHDL and find it difficult to create a testbench for a code. The code will display A5A5 when the input is '00', it will display 12345678ABCDEF when the input is '01', display 500662 wh...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Here you have a testbench for simulate a sychronous circuit. They have 4 process:

1-generates a clock.

2-generates reset. ( probably '0' active ).

3-generates a signal that you don't have.

4-generates a vector input signal. You should adapt it to your code.