Forum Discussion

jrrguzman's avatar
jrrguzman
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

VHDL model for ALTCLKCTRL not generated

Hi, I'm trying to simulate a design with an ALTCLKCTRL clock buffer in it. However, I can't get QSYS to generate the VHDL simulation model. It only does generate Verilog, not matter what settings I ...
Vicky1's avatar
Vicky1
Icon for Regular Contributor rankRegular Contributor
7 years ago

Hi,

Have you resolved the issue?

Check under simulation folder created is ./simulation/.... Instead of submodules.

Let me know if this has helped resolve the issue you are facing or if you need any further assistance.

Best Regards

Vikas Jathar

(This message was posted on behalf of Intel Corporation)