Honored Contributor
Honored ContributorGreetings All:
I hope the simulation is going well. I've used ModeSim a few times, but I usually stick with the Quartus 9.1 simulation, it has no capability of intelligent response to the FPGA's, but it's much faster and easier to run quickly, especially small projects. I notice the code just posted has the 'after 100ns' added, that is used in testbench parts, but if code is targeted to real hardware, such a FPGA/CPLD, it is ignores or causes an error, there's no capability to perform that in most hardware. I put together some information of the the testing I have been doing, take a look. I put up a screenshot showing what happens if I use a different seed. Using seed 5 gets Quartus to place the code's hardware in different logic elements place (compared to seed 9), and that makes the feedback time and path different, and most cause oscillation. I was looking at the actual electronics to see how it maintains the oscillations running even if all inputs are off. The simulation under LTSPICE, if any of RC component is altered, it stabilizes quickly after a few changes. I'm guessing the feedback path inside FPGA's is more complex than the 2-RC stage paths. I have shown a zoom in on the waveforms of the JK flip-flop. Notice the oscillation is off-sided, I couldn't get that to happen under the LTSPICE simulation, it's probably due to the simple feedback paths I made for simulation. Also, the zoom picture shows the propagation delay between clock edge and the response. On the previous simulation shown, take a look zooming on that to see how the propagation delay between the clock and response are in comparison. I noticed the D changes happen at the same as the clock falling edge, there are changes when there is no clock changes (200ns, much beyond hardware propagation), and clock rising with J and K high does not cause the Q toggle as required, like my previous picture showed. I hope all find this is informative. David K.
