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Altera_Forum
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8 years ago

VHDL inout port in gate-level simulation

Hi, I have a design with an bidirectional bus (defined as inout) at the very top level. In module: HWID : inout std_logic_vector(7 downto 0); . . HWID <= data_out ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

Why are you doing gate level simulation? Is there any specific reason you need to?

Ive never done a gate level simulation in 12 years of FPGA design. With good test benches and timing specs/analysis, Ive never needed it