Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorVHDL inout port in gate-level simulation
Hi, I have a design with an bidirectional bus (defined as inout) at the very top level. In module:
HWID : inout std_logic_vector(7 downto 0);
.
.
HWID <= data_out ...
Altera_ForumHonored Contributor
Honored ContributorWhy are you doing gate level simulation? Is there any specific reason you need to?
Ive never done a gate level simulation in 12 years of FPGA design. With good test benches and timing specs/analysis, Ive never needed it
