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Altera_Forum's avatar
Altera_Forum
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8 years ago

VHDL help with code

Hi! Can anyone help me ih writing VHDL code for this diagra? I need simulation results too. Thanks ! :))
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

A0-3 are all outputs, because they have out written next to them.

I highly suggest reading a VHDL tutorial.