VHDL help for using built in Comparators

Thanks for the help.

I mean the comparison result select data to the corresponding port of mem2. Let's say I input the two numbers, which coming out from mem1, into comparator at clock cycle 1. Then the comparison result will come out at clock cycle 2. And I use IF statement to choose the smaller number and send it to port_a at clock cycle 2. But what the IF statement has picked is the comparison result at clock cycle 1 but not clock cycle 2.

The process is like follows:

merg: PROCESS (clock, merg_en)
-------------------------
---some variables ----
-------------------------
IF (rising_edge(clock)) then
     IF (merg_en = '1') then
            ------------- send address to m1 to get number ---------------------
            if (rd_adr_a < 62) then
            m1_rden_a <= '1';
            m1_rden_b <= '1';
            m1_wren_a <= '0';
            m1_wren_b <= '0';
            m1_adr_a <= std_logic_vector(to_unsigned(rd_adr_a, 7));
            m1_adr_b <= std_logic_vector(to_unsigned(rd_adr_b, 7));
            rd_adr_a := rd_adr_a + 2;
            rd_adr_b := rd_adr_b + 2;
        else
            m1_rden_a <= '0';
            m1_rden_b <= '0';
        end if;
            -------------- get m1 feedback, compare, and store to m2 ------------------                    
        if (wr_adr_small < 62) then
            if (rd_delay < 3) then -- 3 clock cycle delay to wait m1 send back data
                rd_delay := rd_delay + 1;
            else
                cp_dataa <= m1_q_a;
                cp_datab <= m1_q_b;
                if (cp_delay < 1) then -- 1 cc omparator delay to wait comparator give result
                    cp_delay := cp_delay + 1;
                else
                    if (cp_eq = '1') then
                        m2_rden_a <= '0';
                        m2_rden_b <= '0';
                        m2_wren_a <= '1';
                        m2_wren_b <= '1';
                        m2_data_a <= cp_dataa;
                        m2_data_b <= cp_datab;
                        m2_adr_a  <= std_logic_vector(to_unsigned(wr_adr_small, 7));
                        m2_adr_b  <= std_logic_vector(to_unsigned(wr_adr_big, 7));
                        wr_adr_small := wr_adr_small + 2;
                        wr_adr_big   := wr_adr_big + 2;
                    elsif (cp_gr = '1') then -- q_a > q_b
                        m2_rden_a <= '0';
                        m2_rden_b <= '0';
                        m2_wren_a <= '1';
                        m2_wren_b <= '1';
                        m2_data_a <= cp_datab;
                        m2_data_b <= cp_dataa;
                        m2_adr_a  <= std_logic_vector(to_unsigned(wr_adr_small, 7));
                        m2_adr_b  <= std_logic_vector(to_unsigned(wr_adr_big, 7));
                        wr_adr_small := wr_adr_small + 2;
                        wr_adr_big   := wr_adr_big + 2;
                    elsif (cp_ls = '1') then -- q_a < q_b
                        m2_rden_a <= '0';
                        m2_rden_b <= '0';
                        m2_wren_a <= '1';
                        m2_wren_b <= '1';
                        m2_data_a <= cp_dataa;
                        m2_data_b <= cp_datab;
                        m2_adr_a  <= std_logic_vector(to_unsigned(wr_adr_small, 7));
                        m2_adr_b  <= std_logic_vector(to_unsigned(wr_adr_big, 7));
                        wr_adr_small := wr_adr_small + 2;
                        wr_adr_big   := wr_adr_big + 2;
        
                    else
            
                    end if;
                end if; -- end delay1cc
            end if; -- end delay3cc        
        end if; -- end rd_adr_a
    end if; -- end merg_en
----------------------------------------
-------- some other things ----------
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end if;