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Altera_Forum's avatar
Altera_Forum
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12 years ago

VHDL Guru needed urgently

Hello Sir,

Am currently working on a temperature sensor for an academic project and the deadline is just too close for me. I have been having challenges with my VHDL code and i need some one to assist me (i'll pay for ur service). Attached is a descriptive document of the work and all the codes that i have written in achieving this. Pls take your time to read through and help me with the correction (pls write out ur own code). Pls dont get upset, am a newbie from an under developed country and nobody here is acquainted with these technology. I had purchased an expensive board already and its too late to change my mind.

In addition, the code compiled successfully, but the challenge is the outputs are all HIGH when i program the device (Stratix III). This is not supposed to be so, since the output is expected to change state with changes in temperature.

Thank you for your time.

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    i suspect i missed the code around the comparator. The gain of the comparator is supposed to be fixed and if it equates the other input to the comparator, then the output counter should stop. But as it is, the output counter counts to the end.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    This is not what an FPGA is for really. I suspect the sysnthesisor is just minimising your delay lines into a single not gate, and therefore no oscilator created. Creating this on an FPGA would be quite involved using RLOCs and specifying exactly what logic blocks to use.

    Good luck.