VHDL global signals

I totally agree that global signals should not be used for actual implementation things - we don't do that and I didn't plan that ;)

The design here is for an ASIC and everything on the FPGA is for debugging/development purposes. For that reason I would have accepted global signals on the FPGA, if that reduces the impact that FPGA elements have on the ASIC code.

And that is the point where I wanted to remove a bunch of signals running through three hierarchies.

But well, Altera probably counts more on customers that do actual design on the FPGAs - and they better don't use these hacks ;)