VHDL global signals

Hi

thanks for the answers. I already changed the code back to normal signals through the hierarchy. I somehow (again...) don't understand what is so difficult about implementing global signals, but I guess there's no choice.

For how I achieved the bidir pins: I think I did nothing else than the straight forward implementation of a package with signals (what by the way is supported according to the quartus help). So that is something like

----------------

<somelibmissinghere>

package foo is

signal bar : std_logic;

end foo;

--------------

Then I used in both top level entity and the one below

-------------

library mylib;

use mylib.foo.all;

------------

That would give a bidir top level pin called something like "*global*bar", where I don't remember the * parts.

Thanks and best regards,

emanuel