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Thank for the great discussion. I am new to FPGA world
My question is let say I have 160 X 120 array of 8 bit registers. This is large. How do figure out the limitations of the FPGA.
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You look at the FPGA specs and make educated guesses. Compile the design and see if you were correct. Usually you are more concerned with RAM or DSP usage as they are easier to estimate than LUT resources.
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Second question x1222 has two for loops in the code. I am assuming that this will synthesize into to large circuit block that executes in one clock cycle.
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Yes, but these are all just parrallel registers as there is no memory between loop iterations.
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