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Thanks for the responses. You guys are right. It is the registers. I lowered it to 70 by 90 and now I hit 28k / 32k of my logic cells. After 8 minutes of compiling my entire program together it is working fine
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I believe you may run into timing problems in hardware (but that depends on your speed). Your inputs XHead,YHead and others enter a massive logic cloud to decide didCollide. You must make sure you choose your set_input_delay correctly and then pass io timing on the path from these inputs to didCollide register.
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In class, we learn about FPGA logic blocks which are look-up tables consisting of a MUX and a flip-flop. Does each logic cell in the DE2 refer to the same thing, or is it a cluster of logic blocks? 8 Bit register = 8 logic cells?
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A basic fpga fabric contains identical units each is a pair of one lut followed by one flipflip (called register usually). The muxes are intrinsic for its configuration and are not for user logic. The user logic is implemented in these luts(not gates). The user may use these pairs as such or only one member of pair with remaining orphan either usable or useless waste.
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I'll see if I use the 160 x 120 matrix using RAM.
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If you run into timing problems then this will save you.
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