VHDL getting Array elements with std_logic_vector

Thanks for the responses. You guys are right. It is the registers. I lowered it to 70 by 90 and now I hit 28k / 32k of my logic cells. After 8 minutes of compiling my entire program together it is working fine

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you say if you remove integer conversion it is fine. I assume by that you mean you declare your inputs as integers, then you can just do that.

But that does not make sense because this conversion is a compile time issue that is settled at compilation and the final logic should be same.

I tried to compile your code and gave same resource whether I do conversions or not. As a side note it tells me that two of your inputs bit 7 are not driving anything.

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I meant removing those conversion lines entirely. I thought it was the integer conversion for the heavy logic cell usage because in the else statement I'm already filling up the matrix with the for loops. So the registers would still be synthesized, that was a bad assumption. In software it would be true, but I'm guessing without the input signals accessing the array the compiler optimizes it and sees the registers aren't accessed and replaces it with some '0' or '1' signals?

In class, we learn about FPGA logic blocks which are look-up tables consisting of a MUX and a flip-flop. Does each logic cell in the DE2 refer to the same thing, or is it a cluster of logic blocks? 8 Bit register = 8 logic cells?

I'll see if I use the 160 x 120 matrix using RAM.