ContributorVHDL Function Overloading not working
I have a VHDL function that is overloaded and works "inconsistently" meaning that sometimes is works and sometimes is just does not.
The general signature of this function is (with return types as overloaded) :
bits(integer, size of result reg) return signed | unsigned | slv
This should work, according to the Quartus handbook which states that subprogram overloading is supported.
I am using Quartus Prime Standard 20.1 for this project, and code snippet is shown below.
Basically, if I initialize a register with some sample code such as:
signed_reg <= bits(500, 16) ;
or
unsigned_reg <= bits(800,16);
or
slv_reg <= bits(250, 16);
I get inconsistent results (without Timing Errors in Quartus) for the register initializations.
I often get for example (showing results in decimal)
signed_reg = 550;
unsigned_reg = 820;
slv_reg = 260;
This is unexplained.
The actual package code is shown below.
Any suggestion or comments are appreciated.
Thanks. James
Nurina,
Thank you for the feedback, this is very helpful.
Basically, if I can summarize your answer, the overloading functions need to have distinct Types for the arguments. From a function signature point of view:
my_function(arg1 : type1) return result type 1
should have an overloaded function type of :
my_function(arge1 : type2) return result type 2
Correct ?
On a background note:
I am updating a code base that someone else developed; I typically would not use overloaded functions. The design intent was to make the VHDL more readable; however I think the basic issue is that the same argument type is present in all three overloaded versions of the function, as you have illustrated. The design is large and there are many functions in packages meant to make the design more readable, however, there are always issues with VHDL conversions if one does not handle them carefully as appears to be the case here.
Thank you and Regards,
James
