Honored ContributorDoes anyone have an example of a DCFIFO in VHDL they would be willing to send or post? Any unrelated code could be deleted but please include anything related to the DCFIFO.
Scott
Honored ContributorOn top of what Dave said - without knowledge of simulation - your job prospects in FPGAs are pretty poor. Its now an essential tool for any engineer to understand and use. Without it, most of the job market will be closed to you..
Honored ContributorAfter looking closer at the input data to the fifo it became apparent the the data was not meeting the setup time. Once that was corrected the fifo works as expected.
ScottHonored ContributorHey Scott,
--- Quote Start --- After looking closer at the input data to the fifo it became apparent the the data was not meeting the setup time. Once that was corrected the fifo works as expected. --- Quote End --- Glad to hear you solved your problem. I still encourage you to take a look a simulation of your design :) Cheers, DaveHonored ContributorDave,
Has the convention changed? When I used to write a lot of code, 15 years ago, signals indicated if they were positive or negative logic. For example, the dcfifo empty flag. It is active low yet the name is "rdempty". We would have called it "nRdEmpty" or something similar to show it was negative logic. ScottHonored ContributorHi Scott,
--- Quote Start --- For example, the dcfifo empty flag. It is active low yet the name is "rdempty". We would have called it "nRdEmpty" or something similar to show it was negative logic. --- Quote End --- No, its not active low. The FIFO is empty when its got nothing in it, and hence the rdempty signal is high. When you write to the FIFO it goes low, as the FIFO is no longer empty. What likely confused you is that the rdempty signal starts out high (active) after a reset, and then goes low (inactive) once written. Cheers, Dave
