Altera_Forum
Honored Contributor
Honored ContributorVHDL equivalence
Hi, I wonder what is the equivalence of this Verilog statement? assign data = (cs && oe && ! we) ? data_out : 8'bz;
Forum Discussion
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- I should have said that the above only applies if you are trying to construct a stand-alone concurrent statement --- Quote End --- That's the same with Verilog assign. It doesn't work in an always block.
