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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL equivalence

Hi, I wonder what is the equivalence of this Verilog statement? assign data = (cs && oe && ! we) ? data_out : 8'bz;
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

Sorry I should have said that the above only applies if you are trying to construct a stand-alone concurrent statement. If this is a line in a process then you need to use an "if" clause, i.e: 

process (clk)
begin
    if rising_edge (clk) then
        if (cs = '1' and oe = '1' and we = '0' ) then
            data <= data_out;
        else
            data <= (others => 'Z');
        end if;
    end if;
end process;