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Altera_Forum's avatar
Altera_Forum
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17 years ago

VHDL equivalence

Hi, I wonder what is the equivalence of this Verilog statement? assign data = (cs && oe && ! we) ? data_out : 8'bz;
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
17 years ago

I'm guessing

data <= data_out when cs = '1' and oe = '1' and we = '0' else (others => 'Z');

I don't personally speak Verilog but I'm guessing that the gist is: when the boolean expression "cs and oe and not we" is 1, assign data_out to data otherwise tri-state data. I hope that's nough to make sense of the VHDL above anyway.