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The first example must implement latches (in a FPGA, they are created as logic loops) to hold the state of the unselected bits. You have at least the problem, that changing the select input can set additional bit's due to glitches, but never reset them. I'm also not sure, if the default expression is synthesized correctly with latches as it works with registers.
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I see. (Only in my terminology a "Latch" is a D-FF, while - as here is no clock - the code only can result in an R/S-FF.) An R/S FF of course can be done using just hogical equations (i.e. gates).
I do see that the code can (or must) be interpreted in the way you mention. So my question is how to be sure that this is not happening. Do I really need to give an "else" with any "when", so that the compiler knows that I don't want a previous result ?
-Michael
Honored Contributor
