VHDL Configuring generics

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The IF GENERATE works, that is the solution i used before askink here. But there are 40 sets of generics, and i do not want to set the Port Map in every generate....So i am searching for a better solution.

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you dont have to. If the port map is the same (like you say) you just do this:

my_ents_gen : for i in 0 to 39 generate
  my_ent : my_entity
  generic map (
    gen0 => GENERICS(i)(0),
    gen1 => GENERICS(i)(1),
    gen2 => GENERICS(i)(2),
    ..etc
  port map (
    ...
    --Do 1 port map once
    ...
  );
end generate my_ents_gen

you only write the code out once.