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Altera_Forum's avatar
Altera_Forum
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8 years ago

VHDL code P2, Is anybody who can help me ?

Hi guys, I have some code for this "project" (photo). I have no idea hot to pair this. Can You help me with port map and signals ? This code is correct ? library IEEE; use IEEE.STD_LOGIC_1164....
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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What do you mean by "attribute signal"?

The code is full of syntax errors and incomplete. So without a reasonable code example, and a specific problem, it is hard to understand what you want....

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My teacher said : Later, you declare a component for the main unit, signals to connections, components and porting mapping ( with no logic describing how works flip flop)

I know its uncomplete but want to know how it works, what is it ? And maybe i wll find code in the internet,I need it now rly, I don't asking for much, only to help with that.