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Altera_Forum's avatar
Altera_Forum
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18 years ago

VHDL code for simple calculation: b = 68 - (a/25)

I want to do a simple calculation in FPGA: b = 68 - (a/25) Anyone help me how can I write VHDL code for this calculation? I try write this code but it fails. Can anybody correct this code? ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

The question is, how quick it is. I found more than 10clocks delay to be setup in the wizzard for are divider in order to be able to calc with the necessary width (48bits in my app) and meet the reqs of the given clock freq.

I wonder what freq could be achieved with a divider of here 10bits in one clock cycle ?