VHDL code error

Hello, I am attaching rest of the code here. Sorry about that.

Test Bench code:

LIBRARY ieee;

USE ieee.std_logic_1164.ALL;

-- Uncomment the following library declaration if using

-- arithmetic functions with Signed or Unsigned values

--USE ieee.numeric_std.ALL;

ENTITY bertb IS

END bertb;

ARCHITECTURE behavior OF bertb IS

-- Component Declaration for the Unit Under Test (UUT)

COMPONENT BERCalculator

PORT(

------------ Clock ----------------------

CLK_IN : in std_logic;

Key : in std_logic_vector (3 downto 0);

------------ SEG7 -----------------------

HEX0 : out std_logic_vector (7 downto 0);

HEX1 : out std_logic_vector (7 downto 0);

HEX2 : out std_logic_vector (7 downto 0);

HEX3 : out std_logic_vector (7 downto 0);

----------- Received_Signals -------------

RX_Received : in std_logic_vector (255 downto 0);

TX_Transmitted : in std_logic_vector (175 downto 0)

);

END COMPONENT;

--Inputs

signal CLK_IN : std_logic := '0';

signal key : in std_logic_vector (3 downto 0) := (others => '1');

signal RX_Received : in std_logic_vector (255 downto 0);

signal TX_Transmitted :in std_logic_vector (175 downto 0)

--Outputs

signal HEX0 : =out std_logic_vector (7 downto 0);

signal HEX1 : out <=std_logic_vector (7 downto 0);

signal HEX2 : out <=std_logic_vector (7 downto 0);

signal HEX3 : out <=std_logic_vector (7 downto 0);

-- Clock period definitions

constant clock_period : time := 20 ns;

BEGIN

-- Instantiate the Unit Under Test (UUT)

uut: up_down_counter PORT MAP (

CLK_IN => CLK_IN,

key => key,

RX_Received => RX_Received,

HEX0=> HEX0,

HEX1=> HEX1,

HEX2=> HEX2,

HEX3=> HEX3,

TX_Transmitted => TX_Transmitted

);

-- Clock process definitions

clock_process :process

begin

CLK_IN <= '0';

wait for clock_period/2;

CLK_IN <= '1';

wait for clock_period/2;

end process;

-- Stimulus process

stim_proc: process

begin

-- hold reset state for 100 ns.

RX_Received: in std_logic_vector (255 downto 0):= (others => '0');

wait for 200 ns;

RX_Received: in std_logic_vector (255 downto 0):= (others => '1');

wait for 100 ns;

TX_Received: in std_logic_vector (175 downto 0):= (others => '1');

wait for 100 ns;

TX_Received: in std_logic_vector (175 downto 0):= (others => '0');

end process;

END;