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Altera_Forum's avatar
Altera_Forum
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13 years ago

VHDL Code and Pin assignments on Terasic TR4

Hello to everyone,

I would like to ask you something about the configuration of pin assignments in VHDL. I would like, before starting to make my question, to say that I am relatively new to VHDL and Quartus II environment, but I have already learned some programming on a DE2 board. I just don´t seem to be able to to the same on the TR4.

I am trying to make an easy blinking LED application, so the first thing I did was to program a VHDL entity called Simple_led, which is taking as input signal an internal 50 Hz oscillator, and it´s letting one of the leds on the board to blink.

Now the code is very easy, I just have somethin like: 

entity Simple_led is
     port(OSC_50_BANK1 : in std_logic;
           LED                 : out std_logic_vector(3 downto 0)
           );
end Simple_led;
architecture behavior of Simple_led is
          
          signal led_c : std_logic := '0';
          
          begin
         
                LED(0) <= led_c;
                
                blink : process(OSC_50_BANK1) 
   
                variable temp : integer := 0;
                begin
                       if (temp = 50000000) then
                            temp := 0;
                            led_c <= not(led_c);
                        else
                            temp := temp + 1;
                        end if;
                end process blink;
end behavior;

The point is that I have defined the pins correctly following the board manual, and I have even checked that on a demonstration design delivered with the board itself.

Inside the pin assignment the clock signal is exaclty called OSC_50_BANK1, and the leds are LED[0], LED[1], LED[2], LED[3].

When I compile the project I get warnings telling me that:

  • there is one pin which is not driving logic....

  • there is no defined clock inside my design...

This is not clear to me. I have verified my design comparing it with the demonstration project which is written in Verilog, but which basically does the same I am doing in VHDL.

Does anyone have an idea why this is happening? In case I can give you more details.

All the best,

Giovanni.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    You should use inside the process a rising_edge(OSC_50_BANK1) to detect the clock rising edge. As I understand you want to increment your variable when you have a clock signal.

    So you would have something like this: 

    
entity Simple_led is
     port(OSC_50_BANK1 : in std_logic;
           LED                 : out std_logic_vector(3 downto 0)
           );
end Simple_led;
architecture behavior of Simple_led is
          
          signal led_c : std_logic := '0';
          
          begin
         
                LED(0) <= led_c;
                
                blink : process(OSC_50_BANK1) 
   
                variable temp : integer := 0;
                begin
                   if rising_edge(OSC_50_BANK1) then
                       if (temp = 50000000) then
                            temp := 0;
                            led_c <= not(led_c);
                        else
                            temp := temp + 1;
                        end if;
                 end if;
                end process blink;
end behavior;