VHDL Code and Pin assignments on Terasic TR4

You should use inside the process a rising_edge(OSC_50_BANK1) to detect the clock rising edge. As I understand you want to increment your variable when you have a clock signal.

entity Simple_led is
     port(OSC_50_BANK1 : in std_logic;
           LED                 : out std_logic_vector(3 downto 0)
           );
end Simple_led;
architecture behavior of Simple_led is
          
          signal led_c : std_logic := '0';
          
          begin
         
                LED(0) <= led_c;
                
                blink : process(OSC_50_BANK1) 
   
                variable temp : integer := 0;
                begin
                   if rising_edge(OSC_50_BANK1) then
                       if (temp = 50000000) then
                            temp := 0;
                            led_c <= not(led_c);
                        else
                            temp := temp + 1;
                        end if;
                 end if;
                end process blink;
end behavior;