Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

VHDL and Transposed Fir

Hello guys , I'm implementing a transposed fir filter in vhdl in which only the sum are pipelined. The code I wrote up (using this (http://www.google.it/url?sa=t&rct=j&q=&esrc=s&source=web...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
11 years ago

to get initial values correctly you need to set accumulators to zero start.

you are scaling by discarding 19 bits. Is that what you wanted?