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Altera_Forum
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8 years ago

[VHDL] alias usage for referencing of the hierarchical signals

Hi All, I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design): # ** Warning: (vsim-8523) C...
Altera_Forum's avatar
Altera_Forum
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8 years ago

Also, you can alias an alias, but and alias takes the form of the thing its aliasing. So an alias to a signal is a signal, alias to a variable is a variable etc.