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Altera_Forum's avatar
Altera_Forum
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8 years ago

[VHDL] alias usage for referencing of the hierarchical signals

Hi All, I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design): # ** Warning: (vsim-8523) C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

The alias is scoped like anything else. If you create an alias in a process, then it is only available inside that process. BUT, you can use external names to access these from outside the process.

Also remember you can declare signals inside a generate, so you could do this: 


mygen : if true generate
  alias a  is << something >>;
begin
  -- alias now visible throughout generate
end generate mygen;