Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

[VHDL] alias usage for referencing of the hierarchical signals

Hi All, I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design): # ** Warning: (vsim-8523) C...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

What's a scope of the aliases? Could it be visible from other hierarchies?