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Altera_Forum
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8 years ago

[VHDL] alias usage for referencing of the hierarchical signals

Hi All, I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design): # ** Warning: (vsim-8523) C...
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Altera_Forum
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8 years ago

An alias can be placed anywhere. So an alias to a signal can be declared in a architecture, process, procedure or any other declarative region.

Because you must declare them after the entity declaration, you are basically forced to declare them inside processes.