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Altera_Forum
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8 years ago

[VHDL] alias usage for referencing of the hierarchical signals

Hi All, I'm receiving the following error message while my VHDL code compilation (actually the compilation has passed, this error appears during load_design): # ** Warning: (vsim-8523) C...
Altera_Forum's avatar
Altera_Forum
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8 years ago

OK, in some place on the web I have read that the alias should be declared after an instance it refers to. This way the signal will be elaborated before it's referenced.

But how to do so? It's not possible to put an alias declaration inside of the process. Is there a way to declare an alias in the architecture body after instantiation of the referenced entity?