VHDL : Problem with 4-Bit Adder and Subtractor !

I want to make a 4-Bit Adder and Subtractor with VHDL

I have created 1-Bit Full-Adder , XOR Gate ( for Subtract ) and a 4-Bit Adder as shown below :

Full-Adder :


LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY FullAdder_1_Bit IS   PORT(     X, Y : IN STD_LOGIC;     CIn  : IN STD_LOGIC;     Sum  : OUT STD_LOGIC;     COut : OUT STD_LOGIC   ); END FullAdder_1_Bit;  ARCHITECTURE Behavier OF FullAdder_1_Bit IS BEGIN   Sum <= X XOR Y XOR CIn;   COut <= (X AND Y) OR (X AND CIn) OR (Y AND CIn); END Behavier;

XOR Gate :


LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY XORGate IS   PORT(     X1, X2 : IN STD_LOGIC;     Y : OUT STD_LOGIC   );   END XORGate;  ARCHITECTURE Declare OF XORGate IS BEGIN    Y <= X1 XOR X2; END Declare;

4-Bit Adder :


LIBRARY ieee; USE ieee.std_logic_1164.all;  ENTITY Adder_4_Bit IS   PORT(     A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);     Mode : IN STD_LOGIC;     Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);     COut : OUT STD_LOGIC   );   END Adder_4_Bit;  ARCHITECTURE Structure OF Adder_4_Bit IS COMPONENT FullAdder_1_Bit IS   PORT(     X, Y : IN STD_LOGIC;     CIn  : IN STD_LOGIC;     Sum  : OUT STD_LOGIC;     COut : OUT STD_LOGIC   ); END COMPONENT;  COMPONENT XORGate IS   PORT(     X1, X2 : IN STD_LOGIC;     Y : OUT STD_LOGIC   );   END COMPONENT;  SIGNAL COut_Temp : STD_LOGIC_VECTOR(2 DOWNTO 0); SIGNAL XB : STD_LOGIC_VECTOR(3 DOWNTO 0);  BEGIN     B_0 : XORGate PORT MAP(Mode, B(0), XB(0));   B_1 : XORGate PORT MAP(Mode, B(1), XB(1));   B_2 : XORGate PORT MAP(Mode, B(2), XB(2));   B_3 : XORGate PORT MAP(Mode, B(3), XB(3));    SUM_0 : FullAdder_1_Bit   PORT MAP (A(0), XB(0), Mode, Sum(0), COut_Temp(0));    SUM_1 : FullAdder_1_Bit   PORT MAP (A(1), XB(1), COut_Temp(0), Sum(1), COut_Temp(1));    SUM_2 : FullAdder_1_Bit   PORT MAP (A(2), XB(2), COut_Temp(1), Sum(2), COut_Temp(2));    SUM_3 : FullAdder_1_Bit   PORT MAP (A(3), XB(3), COut_Temp(2), Sum(3), COut);   END;

and in my Main Codes , i have used those ( like Test-Bench ! ) :


LIBRARY ieee; USE ieee.std_logic_1164.all; USE ieee.std_logic_unsigned.ALL;  ENTITY Add_AND_Sub IS  END Add_AND_Sub;  ARCHITECTURE Declare OF Add_AND_Sub IS COMPONENT Adder_4_Bit IS   PORT(     A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);     Mode : IN STD_LOGIC;     Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);     COut : OUT STD_LOGIC   );   END COMPONENT;  SIGNAL A, B : STD_LOGIC_VECTOR(4 DOWNTO 0); SIGNAL Mode : STD_LOGIC; SIGNAL As, Bs, E, AVF : STD_LOGIC; SIGNAL XA, XB, Sum : STD_LOGIC_VECTOR(3 DOWNTO 0);  BEGIN    Add : Adder_4_Bit  PORT MAP(XA, XB, Mode, Sum, E);   PROCESS(A, B, Mode)  BEGIN   As <= A(4);   Bs <= B(4);    XA <= A(3 DOWNTO 0);   XB <= B(3 DOWNTO 0);      CASE Mode IS    WHEN '0' =>      IF ((As XOR Bs) = '1') THEN                           Mode <= '1';        XA <= Sum;               AVF <= '0';        IF (E = '1') THEN          IF (XA = "0000") THEN            As <= '0';          END IF;        ELSE                     XA <= (NOT XA) + "0001";          As <= NOT As;        END IF;       ELSE        XA <= Sum;      END IF;        WHEN '1' =>      IF ((As XOR Bs) = '1') THEN                      Mode <= '0';               XA <= Sum;               AVF <= E;              ELSE               AVF <= '0';        XA <= Sum;        IF (E = '1') THEN          IF (XA = "0000") THEN            As <= '0';          END IF;        ELSE          XA <= (NOT XA) + "0001";          As <= NOT As;        END IF;            END IF;    WHEN Others =>       --      END CASE;            END PROCESS;   END Declare;

The main scenario is to Model this algorithm :

http://i.stack.imgur.com/3H6hv.jpg

but now i want to have output in XA and As

I Should use registers shown in algorithm such as "E" and "AVF"

there is one question :

we know port maps are continuously connected , so when i change "Mode" Value , Result ( Sum ) must change , is it True ?!

I have tried this code but i cant get output in XA , and there is no True result for sum values , i know there is some problem in my main code ( Process ) , but i cant find problems

please check that codes and tell me what goes wrong !

thanks ...

11 Replies

Altera_Forum

Honored Contributor

11 years ago

New ALU :


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Cs : IN STD_LOGIC;
    Ds : IN STD_LOGIC;
    Mode_ALU : IN STD_LOGIC;
    Sum_ALU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    AVF : OUT STD_LOGIC    
  );
END ALU;
ARCHITECTURE Declare OF ALU IS
COMPONENT Adder_4_Bit IS
  PORT(
    A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Mode : IN STD_LOGIC;
    Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    COut : OUT STD_LOGIC
  );  
END COMPONENT;
SIGNAL E, Temp_Cs, Temp_Ds : STD_LOGIC;
SIGNAL Temp_S : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN   
  
 Add : Adder_4_Bit PORT MAP(C, D, Mode_ALU, Temp_S, E);   
 
-- Sum_ALU <= Temp_S;
-- Temp_Cs <= Cs;
-- Temp_Ds <= Ds;
 PROCESS
 BEGIN
  WAIT FOR 30 ns;
  
  Sum_ALU <= Temp_S;
  Temp_Cs <= Cs;
  Temp_Ds <= Ds;
 END PROCESS; 
 PROCESS(C, D, Cs, Ds, Mode_ALU)
 BEGIN   
  
  CASE Mode_ALU IS
   WHEN '0' =>
     IF ((Cs XOR Ds) = '1') THEN                                
       AVF <= '0';
       IF (E = '1') THEN
         IF (Temp_S = "0000") THEN
           Temp_Cs <= '0';
         END IF;
       ELSE           
         Sum_ALU <= (NOT Temp_S) + "0001";
         Temp_Cs <= NOT Cs;
       END IF;
     ELSE
       AVF <= E;
     END IF;
        
   WHEN '1' =>
     IF ((Cs XOR Ds) = '1') THEN                                  
       AVF <= E;        
     ELSE       
       AVF <= '0';
       IF (E = '1') THEN
         IF (Temp_S = "0000") THEN
           Temp_Cs <= '0';
         END IF;
       ELSE
         Sum_ALU <= (NOT Temp_S) + "0001";
         Temp_Cs <= NOT Cs;
       END IF;      
     END IF;
     
   WHEN Others =>  
    --   
  END CASE;
            
 END PROCESS; 
  
END Declare;

New Test Bench :


LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU_Test_Bench IS
 
END ALU_Test_Bench;
ARCHITECTURE Declare OF ALU_Test_Bench IS
COMPONENT ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Cs : IN STD_LOGIC;
    Ds : IN STD_LOGIC;
    Mode_ALU : IN STD_LOGIC;
    Sum_ALU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    AVF : OUT STD_LOGIC    
  ); 
END COMPONENT;
SIGNAL Xs, Ys, M, Av : STD_LOGIC;
SIGNAL X, Y, O : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  
  ALU_PM : ALU PORT MAP(X, Y, Xs, Ys, M, O, Av);
 
  Mode_Process : PROCESS
  BEGIN
  M <= '1';
  WAIT FOR 10 ns;
  
  M <= '0';
  WAIT FOR 10 ns;
    
  END PROCESS;
  
  Calc_Process : PROCESS
  BEGIN       
     
   X <= "0010";
   Y <= "1011";
   Xs <= '0';
   Ys <= '1';
   WAIT FOR 20 ns;
   
   X <= "0110";
   Y <= "0011";
   Xs <= '1';
   Ys <= '1'; 
   WAIT FOR 20 ns; 
    
   X <= "0010";
   Y <= "1011";
   Xs <= '0';
   Ys <= '1';
   WAIT FOR 20 ns; 
      
  END PROCESS;
  
END Declare;

But the Result have 'X' Value ! :

https://www.alteraforum.com/forum/attachment.php?attachmentid=10765

Is the Process I have written in ALU for setting temp values, correct ?

thank for your help Tricky ...

Forum Discussion

VHDL : Problem with 4-Bit Adder and Subtractor !

11 Replies

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