VHDL : Problem with 4-Bit Adder and Subtractor !

New ALU :

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Cs : IN STD_LOGIC;
    Ds : IN STD_LOGIC;
    Mode_ALU : IN STD_LOGIC;
    Sum_ALU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    AVF : OUT STD_LOGIC    
  );
END ALU;
ARCHITECTURE Declare OF ALU IS
COMPONENT Adder_4_Bit IS
  PORT(
    A, B : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Mode : IN STD_LOGIC;
    Sum  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    COut : OUT STD_LOGIC
  );  
END COMPONENT;
SIGNAL E, Temp_Cs, Temp_Ds : STD_LOGIC;
SIGNAL Temp_S : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN   
  
 Add : Adder_4_Bit PORT MAP(C, D, Mode_ALU, Temp_S, E);   
 
-- Sum_ALU <= Temp_S;
-- Temp_Cs <= Cs;
-- Temp_Ds <= Ds;
 PROCESS
 BEGIN
  WAIT FOR 30 ns;
  
  Sum_ALU <= Temp_S;
  Temp_Cs <= Cs;
  Temp_Ds <= Ds;
 END PROCESS; 
 PROCESS(C, D, Cs, Ds, Mode_ALU)
 BEGIN   
  
  CASE Mode_ALU IS
   WHEN '0' =>
     IF ((Cs XOR Ds) = '1') THEN                                
       AVF <= '0';
       IF (E = '1') THEN
         IF (Temp_S = "0000") THEN
           Temp_Cs <= '0';
         END IF;
       ELSE           
         Sum_ALU <= (NOT Temp_S) + "0001";
         Temp_Cs <= NOT Cs;
       END IF;
     ELSE
       AVF <= E;
     END IF;
        
   WHEN '1' =>
     IF ((Cs XOR Ds) = '1') THEN                                  
       AVF <= E;        
     ELSE       
       AVF <= '0';
       IF (E = '1') THEN
         IF (Temp_S = "0000") THEN
           Temp_Cs <= '0';
         END IF;
       ELSE
         Sum_ALU <= (NOT Temp_S) + "0001";
         Temp_Cs <= NOT Cs;
       END IF;      
     END IF;
     
   WHEN Others =>  
    --   
  END CASE;
            
 END PROCESS; 
  
END Declare;

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE ieee.numeric_std.all;
USE ieee.std_logic_unsigned.ALL;
ENTITY ALU_Test_Bench IS
 
END ALU_Test_Bench;
ARCHITECTURE Declare OF ALU_Test_Bench IS
COMPONENT ALU IS
  PORT(
    --Clk  : IN STD_LOGIC;
    C : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    D : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
    Cs : IN STD_LOGIC;
    Ds : IN STD_LOGIC;
    Mode_ALU : IN STD_LOGIC;
    Sum_ALU : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
    AVF : OUT STD_LOGIC    
  ); 
END COMPONENT;
SIGNAL Xs, Ys, M, Av : STD_LOGIC;
SIGNAL X, Y, O : STD_LOGIC_VECTOR(3 DOWNTO 0);
BEGIN
  
  ALU_PM : ALU PORT MAP(X, Y, Xs, Ys, M, O, Av);
 
  Mode_Process : PROCESS
  BEGIN
  M <= '1';
  WAIT FOR 10 ns;
  
  M <= '0';
  WAIT FOR 10 ns;
    
  END PROCESS;
  
  Calc_Process : PROCESS
  BEGIN       
     
   X <= "0010";
   Y <= "1011";
   Xs <= '0';
   Ys <= '1';
   WAIT FOR 20 ns;
   
   X <= "0110";
   Y <= "0011";
   Xs <= '1';
   Ys <= '1'; 
   WAIT FOR 20 ns; 
    
   X <= "0010";
   Y <= "1011";
   Xs <= '0';
   Ys <= '1';
   WAIT FOR 20 ns; 
      
  END PROCESS;
  
END Declare;