VGA sync circuit

Creating a testbench is always the first step after writing the code, before you even get to the FPGA, to test the operation of the design under test.

For you testbench, you dont have to write synthesisable code, you can just write behavioural code. For example, here is how you would define a basic clock for a testbench

signal clk : std_logic := '1';
....
clk <= not clk after 5 ns; --100 MHz clock

or maybe some hand crafted waveform:

process
begin
  input <= 1;
  for i in 1 to 10 loop
    wait until rising_edge(clk);
  end loop;
  
  input <= 2;
  wait for 1 ms;
  input <= 3;
  wait;
end process;