VGA DE2 VGA_Drive

HII

Ill try to convert VGA driver to DE2 bord on VHDL but it dosnt work

ill post my code maybe you have any idea

thanks

dana

code:

--------------------Title-------------------------------------

--Project Name: VGA_Controller

--File Name: VGA_Driver.vhd

--------------------------------------------------------------

library ieee;

use ieee.std_logic_1164.all;

--------------------------------------------------------------

-------------------------Entity-------------------------------

entity VGA_Driver is

port(

clock : IN std_logic; --5MHz

reset : IN std_logic;

RGB_In : IN std_logic_vector (2 downto 0);

Red : OUT std_logic_vector (3 downto 0);

Green : OUT std_logic_vector (3 downto 0);

Blue : OUT std_logic_vector (3 downto 0);

H_Sync : OUT std_logic :='1';

V_Sync : OUT std_logic :='1';

sync : out std_logic ;

VGA_CLK : out std_logic;

blank : out std_logic

);

end VGA_Driver;

------------------------------------------------------------

--------------------Architecture----------------------------

architecture behave of VGA_Driver is

------------------------------------------------------------

---------------COMPONENTS DECLARATION-----------------------

COMPONENT VGA_PLL IS

PORT

(

areset : IN STD_LOGIC := '0';

inclk0 : IN STD_LOGIC := '0';

c0 : OUT STD_LOGIC ;

locked : OUT STD_LOGIC

);

END COMPONENT;

------------------------------------------------------------

----------------Signals Declaration-------------------------

signal s_locked : STD_LOGIC;

signal clock_25MHZ : STD_LOGIC:= '0';

------------------------------------------------------------

-------------COMPONENTS INSTANTIATION-----------------------

begin

--U1:VGA_PLL

--PORT MAP

-- (

-- areset => reset,

-- inclk0 => clock,

-- c0 => clock_25MHZ,

-- locked => s_locked

-- );

------------------------------------------------------------

sync <= '0';

--VGA_CLK <= clock_25MHZ;

blank <= '1';

process(clock_25MHZ,reset)

variable H_Count:integer range 0 to 799;

variable V_Count:integer range 0 to 524;

begin

if reset='1'

then H_Count :=0;

V_Count :=0;

H_Sync <='1';

V_Sync <='1';

--blank <= '1';

elsif clock_25MHZ' EVENT and clock_25MHZ='1'

then

--sync <= '1';

--blank <= '0';

H_Count:=H_Count+1;

if (H_Count=799) then

H_Count:=0;

V_Count:=V_Count+1;

end if;

if(V_Count=524) then

V_Count:=0;

end if;

--end if;

-------------------------------------------------------

--------Horizontal Sync Signals------------------------

case H_Count Is

when 0 to 95 =>

H_Sync <='0';

Red <=(others =>'0');

Green <=(others =>'0');

Blue <=(others =>'0');

-- blank <= '1';

when 96 to 143 =>

H_Sync <='1';

Red <=(others =>'0');

Green <=(others =>'0');

Blue <=(others =>'0');

--blank <= '0';

when 144 to 783 =>

H_Sync <='1';

Red <=(others => RGB_In(2));

Green <=(others => RGB_In(1));

Blue <=(others => RGB_In(0));

--blank <= '1';

when 784 to 799 =>

H_Sync <='1';

Red <=(others =>'0');

Green <=(others =>'0');

Blue <=(others =>'0');

-- blank <= '0';

end case;

------------------------------------------------------

--------Vertical Sync Signals-------------------------

case V_Count Is

when 0 to 1 =>

V_Sync <='0';

Red <=(others =>'0');

Green <=(others =>'0');

Blue <=(others =>'0');

--blank <= '1';

when 2 to 34 =>

V_Sync <='1';

Red <=(others =>'0');

Green <=(others =>'0');

Blue <=(others =>'0');

--blank <= '0';

when 35 to 514 =>

V_Sync <='1';

--blank <= '1';

when 515 to 524 =>

V_Sync <='1';

Red <=(others =>'0');

Green <=(others =>'0');

Blue <=(others =>'0');

-- blank <= '0';

end case;

-------------------------------------------------------

end if;

end process;

vga_clk_gen : PROCESS(clock,reset)--devides 50MHz clock in 2, making it a 25MHz clock

VARIABLE count : INTEGER := 0;

BEGIN

IF reset= '1' THEN

clock_25MHZ <= '0';

VGA_CLK <= '0';

count := 0;

ELSIF rising_edge(clock) THEN

IF count = 0 THEN

clock_25MHZ <= '1'; --1 period of 50MHz high

VGA_CLK <= '1';

count := 1;

ELSIF count = 1 THEN

clock_25MHZ <= '0'; --1 period of 50MHz low

VGA_CLK <= '0';

count := 0;

END IF;

END IF;

END PROCESS;

end behave;