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Honored ContributorVGA controller help
I am trying to code pong and I am having trouble syncing up the monitor. I am using a DE2 alterra board and when i run the code the monitor acts like it is not receiving anything. I am using a block diagram and having a 25MHz clock as an input coming into this code. Thanks for the help.
Here is my code: library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.std_logic_unsigned.all; entity vga_controller is port( clk, reset: in std_logic; red, green, blue: in std_logic; red_out, green_out, blue_out : out std_logic; hsync, vsync, blank: out std_logic; pixel_row, pixel_col: out std_logic_vector (9 downto 0) ); end vga_controller; architecture sync of vga_controller is signal video_on, vvideo_on, hvideo_on : std_logic; signal hcount, vcount : std_logic_vector (9 downto 0); begin video_on <= vvideo_on and hvideo_on; blank <= video_on; process (clk, reset) begin if reset = '1' then hcount <= "0000000000"; elsif (clk'EVENT and clk='1') then if hcount = 799 then hcount <= "0000000000"; else hcount <= hcount +1; end if; end if; end process; process (hcount) begin if hcount<639 then hvideo_on <= '1'; pixel_col <= hcount; else hvideo_on <= '0'; pixel_col <= "0000000000"; end if; end process; process (clk, reset) begin if reset = '1' then vcount <= "0000000000"; elsif (clk'EVENT and clk='1') then if vcount = 524 and hcount = 699 then vcount <= "0000000000"; else vcount <= vcount +1; end if; end if; end process; process (vcount) begin if vcount<479 then vvideo_on <= '1'; pixel_row <= vcount; else vvideo_on <= '0'; pixel_row <= "0000000000"; end if; end process; process (clk, reset) begin if reset = '1' then hsync <= '0'; vsync <= '0'; elsif (clk'EVENT and clk='1') then if hcount<= 755 and hcount >= 659 then hsync <= '0'; else hsync <= '1'; end if; if vcount<= 494 and vcount >= 493 then vsync <= '0'; else vsync <='1'; end if; end if; end process; process (clk, reset) begin if reset <= '1' then red_out <= '0'; green_out <= '0'; blue_out <= '0'; elsif (clk'EVENT and clk='1') then red_out <= red and video_on; green_out <= green and video_on; blue_out <= blue and video_on; end if; end process; end sync;
