very strange QuartusII 7.1 synthesis Tool results

Take a look at the PSELx signals – they feed the register file read MUXes in APBS1..3, out to the “Mux2SM” data inputs. They also feed the MUX2Sm selects, generated from the Arbiter. The reconvergence makes them partially redundant. Notice that for example PRDATA3 won’t be visible to the outputs unless PSELS3 is high. PSELS3 (on port PSEL) is also used as an enable within APBS3.v - that can be minimized out as a don’t care.

As Brad and Rysc pointed out the data are given an unintended priority relationship by the Verilog case statement (even though they are actually one hot). It appears that the priority order change in “better”, “best”, “worst” is enough to jog the synthesis into recognizing more or fewer redundancies. It is probably hitting a depth limit in the minimization heuristics.

If you edit the arbiter like so …

wire common_sel = PSEL & (PADDR[15:10] == 6'b000000) /* synthesis keep */;

always@(*) begin

PSELS1 = common_sel & (PADDR[9:8] == 2'h1);

PSELS2 = common_sel & (PADDR[9:8] == 2'h2);

PSELS3 = common_sel & (PADDR[9:8] == 2'h3);

//PSELD is not used by the MUX in the current arrangement

PSELD = 1'b0;

end

The best and worst behaviors converge to the ‘best’ result in my Quartus. Fewer signals for minimization and clock enables to squabble over. For the long haul you probably want to edit out the extra read selects.