very strange QuartusII 7.1 synthesis Tool results

One last thing about what's going "heuristics". Maybe in the small test case, it realizes such a large percentage of the logic is using clock enables and it might have trouble packing them into labs, so it decides to use logic for this hierarchy, which seems logical. But once you put more logic into the design, it may switch back to using the clock enable. So it might be worthwhile to put this on the backburner for a while.

And in reality, I would try to get these into M512 RAMs. This will soak up all the flip-flops and all the addressing logic, and my guess is your design will reduce to ~6 M512s and a few hundred LUTs. The reason it won't go in now is that every flop/cell of the memory has a reset signal that can reset it to a specific value. This can't be implemented in embedded memory, although you can have an initialization file, so that it powers up to a specific state(you just can't reset into it). If you really, really need to be able to reset them, you might be able to have "shadow M512s" that hold those values, and on reset their values get dumped into your working RAMs. Just some ideas.