very strange QuartusII 7.1 synthesis Tool results

How many LUTs did ISE use? Note that these are not the same statements in verilog, as the case statement is treated as a priority encoder, essentially a chain of if... else if... else if... statements. So if PSEL1 and PSEL3 are both active, then the first case and the second case will produce different results. Synthesis tools will try to determine if the cases are mutually exclusive, but that might not be possible if it's a one-hot signal that is decoded in another hierarchy. There are directives to get around this(parallel_case), which might help. Also look at the results and try to determine what was synthesized out and if it makes sense.