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Altera_Forum
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13 years ago

Very slow clock signals and STA in TimeQuest

For some specific usage, I need some very slow clock signals. They are generated from FPGA for outside chip. For example, the FPGA clock is 40Mhz, so clock period is 25ns and I named this cloc...
Altera_Forum's avatar
Altera_Forum
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13 years ago

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check out the clock network docs for your particular architecture. it will list what type of clock regions are available.

you get peripheral clocks (pclk), regional, dual-regional, and global (did I miss any?). I'm not sure by default what the tool will choose if you leave the altclkctrl as "AUTO", because it probably depends on the fanout.

Make sure you look at timing too. globals will help fanout in a large design, but you usually sacrifice time spent getting to and from the clock networks. I have had many designs have better results with regional or dual-regional clocks.

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Thanks. you mentioned "check out the clock network docs for your particular architecture", do you mean the doc from Altera for specific FPGA chip? For example, I use Cyclone IV E family FPGA, I should check the document for them, right?