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Altera_Forum
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13 years ago

Very slow clock signals and STA in TimeQuest

For some specific usage, I need some very slow clock signals. They are generated from FPGA for outside chip. For example, the FPGA clock is 40Mhz, so clock period is 25ns and I named this cloc...
Altera_Forum's avatar
Altera_Forum
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13 years ago

Using a counter is usually fine for such a slow clock, as long as you constrain it with the create_generated_clock constraint. The tools will typically drive it through a clock buffer (altclkctrl), or you can do it manually. Alternatively you could cascade plls, but you'll need to phase align it to the fast clock when you do transfers