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Altera_Forum
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16 years ago

Very different simulation results of a simple counter

Hello I'm in my third year bachelor electronics and i'm making a project in vhdl. In this project there is a simple counter that should start counting at zero. The counter has 4 selection outpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

The synthesisor usually takes the asynchronous reset value as the power up state rather than the initial assignment you have given it.