Very different simulation results of a simple counter

The reason for it is because i want the counter to start at 0000 on the first clockpulse. The counter is connected to a multiplexer and i want it to start at the beginning. Now the counter will count to 0001 on the first pulse but on the output i put 0000. Maby there are better ways to do this, my vhdl knowledge is rather limited actually.

I will try to change the reset, thank you.

edit : I can't belive it, the reset was the problem. I thought it had nothing to do with it. The fact it worked good on the cyclone 1 made me confused.

Thanks alot for your help!