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Altera_Forum's avatar
Altera_Forum
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16 years ago

Very different simulation results of a simple counter

Hello I'm in my third year bachelor electronics and i'm making a project in vhdl. In this project there is a simple counter that should start counting at zero. The counter has 4 selection outpu...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

I would put those lines:

if (tmp="1001") then 
tmp <= "0001";
inside the clocked event. I'm not sure how the synthesizer will read your code, but it could identify those two lines as an asynchronous reset.

Keep everything synchronous and it will work better.

Is there any reason why you want to keep an internal counter and put its value minus one on the output?