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Altera_Forum's avatar
Altera_Forum
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18 years ago

Vertical and Horizontal Sync Signal

does anyone know how to write the code in VHDL by using Quartus 2 to control or generate these two signal?? i need to use it to generate color on the CRT monitor screen.. how does the code look...
Altera_Forum's avatar
Altera_Forum
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18 years ago

Moin,

I've not done anything like this yet, but i'd say, that you'd need conters anyway for addressing the Memory, where your pixeldata is located. Generating from this counter(s) the H/V Sync signals should be mor or less just a by-product.

The counters do have to count for more than just the desired number of displayed pixel to get the time for blanking and the sync signal itself.

Example: Timing of one line of PAL video:

One line including flyback takes 64usec and might e.g. consist of 864 cycles with 1/13.5MHz each. In this line there are 720 pixel read out, blanking takes the rest (that's 864-720=144 cycles). Within the blanking period, the H-Sync must be generated with a length of 64 cycles... In this case, the H-sync pulse ususally is low during the sync, so it's more a /H-Sync than a H-Sync.

What kind of Video/Sync signal do you want to generate? Interlaced/Non-Interlaced? Which resolution? Which frequencies? Composite oder seperate Sync...?

Cheers

WK