Verilog

You're thinking like a software engineer and not a hardware designer. For an FPGA design, you want to create counter hardware that counts up to what you want (a modulus counter) and then can send a signal out that indicates that count is complete and perhaps use the same output signal to start the next counter. A modulus 100 counter for this could look like:

module count 
	#(parameter modulus = 100)
	(
	input clock, aclr_n,
	output reg [7:0] q = 0
);

reg count100complete;

always @(posedge clock, negedge aclr_n) 
begin
	if (aclr_n == 0) begin
		q[7:0] <= 0;
                count100complete <= 1'b0;
        end
	else begin
		if (q == modulus - 1) begin
			q <= 8’d0;
                        count100complete <= 1'b1;
                end
		else
			q <= q + 1;
	end
end
endmodule

Then you could do an if check on count100complete in another always block that starts the next counter if you're chaining them together and as an indicator that 100 cycles of whatever you are trying to perform is complete.

If you do need to make use of the incrementing index value and not just for timing a certain number of cycles, you could incorporate for loops as you've mentioned separate from this counter logic.