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Altera_Forum
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15 years ago

Verilog XOR issue

Hi All, I have a working piece of code : if(in_I & in_Q) cnt <= cnt + `INC_SIZ; if(in_I & !in_Q) cnt <= cnt - `INC_SIZ; if(!in_I & in_Q) cnt <= cnt - `INC_SIZ; if(!in_I & !in_Q) ...
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Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Arrgh, busted hardware !

That was quite a waste of a few hours.

The problem really smelt like a compiler bug.

Change to new hardware and everything looks OK.

Regards,

Mark