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Altera_Forum
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15 years ago

Verilog XOR issue

Hi All, I have a working piece of code : if(in_I & in_Q) cnt <= cnt + `INC_SIZ; if(in_I & !in_Q) cnt <= cnt - `INC_SIZ; if(!in_I & in_Q) cnt <= cnt - `INC_SIZ; if(!in_I & !in_Q) ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Your first logic is equivalent to this below:

if(in_I ^ in_Q) begin cnt <= cnt - `INC_SIZ; end

else begin cnt <= cnt + `INC_SIZ; end